The constantly increasing number of electrical connections between wafers and their carrier elements, and in particular the miniaturization required to obtain flattest possible assemblies, has led to the use of direct electrical bonding of the semiconductor chips on the carrier elements (flip-chip bonding).
However, to permit direct bonding of semiconductor chips on carrier elements, such as a PCB (printed circuit board), it is desirable to produce on the semiconductor chip 3-D structures which end at their respectively highest point in a gold-plated contact area and are connected to the bond pad of the wafer via a reroute trace. This gold-plated contact area may then be provided with a micro-ball, or the like, of a solder material and be electrically and mechanically connected to a corresponding soldering contact on the PCB.
To achieve a certain compensation for mechanical loads of the finished assembly, caused for example by different coefficients of thermal expansion of the individual components, the base element of the 3-D structure is produced from a compliant material, for example silicone, so that after its metallization a three-dimensional, mechanically flexible structure which is firmly connected to the wafer is produced.
The reroute traces used for the electrical connection between the bond pad and the 3-D structure are built up on a seed layer, on which a copper reroute trace is grown and a nickel layer is grown on top. The nickel layer protects the copper layer from corrosion. Under the seed layer and the base element there is generally a dielectric, so that it is ensured that an electrical connection exists only between the contact element on the 3-D structure and the associated bond pad.
To achieve solderability of the contact element, the nickel layer should be coated in this region with gold, at least on the tip of the 3-D structure.
In the case of a method for the structuring of 3-D structures that is currently used in practice, the necessary structuring of the gold layer is realized by a generally known lithographic process. The structuring of the functional elements takes place here by the gold being deposited on the entire redistribution layer following the deposition of the seed layer and the copper/nickel layer. After that, the gold layer is covered by a lithographic process in such a way that selective etching or stripping of the undesired regions of the gold layer can take place and, when completed, a gold layer only remains in the region of the 3-D structure. The 3-D structure produced in this way is to be referred to hereafter as the functional 3-D structure, since it is essential for the electrical bonding of the chips, individually separated from the wafer, with carrier elements.
This method can be summarized by the following process sequence:
depositing of the seed layer;
EPR1 (Epoxy Photoresist 1): coating and structuring (lithographic step 1);
reroute plating, producing the copper/nickel layer on the seed layer;
coating of the reroute trace with gold;
EPR2 (Epoxy Photoresist 2): coating and structuring (lithographic step 2);
selective etching of the gold layer; and
wet etching or stripping.
However, the functional 3-D structures produced by this method must be tested for their functional capability in the wafer assembly, that is before they are separated into individual chips. For this purpose, the wafer must be fed to a testing device in which all the functional 3-D structures can be electrically bonded simultaneously, i.e., so that an electrical contact with a test circuit is established. In this respect it must be ensured that the compliant functional 3-D structures are on the one hand brought into contact with the testing device with adequate force, but on the other hand are not mechanically overloaded or destroyed. It must consequently be ensured that the wafer is placed onto the testing device under defined conditions.
A further problem associated with the use of compliant functional 3-D structures is the quite high sensitivity to damage when they are being handled, e.g., during transport or during intermediate storage.
After the separation of the wafers into individual chips and their soldering to a carrier element, the functional 3-D structures are protected by the carrier element. This means that the sensitive functional 3-D structures primarily have to be protected from damage in the wafer assembly, e.g., before individual separation.